Chisel: Constructing Hardware in a Scala Embedded Language

https://chisel.eecs.berkeley.edu/index.html

by archgoon • 11 years ago

57 58 11 years ago

chisel.eecs.berkeley.edu

minthd2• 11 years ago

They claim this language is highly parameterized. I wonder how much.

For example can you design a generic processor in such a way that everything will be parameterized?

rjsw• 11 years ago

They use this language for RISC-V, if you look at the sources you can see the kind of things that can be parameterized.

cmrx64• 11 years ago

I've been playing with this for the past few weeks. It's a lot of fun compared to Verilog or VHDL. The implementation is still young, though, and it's pretty easy to trigger an undecipherable crash. But I haven't had anything miscompile yet.

ci5er• 11 years ago

I'm trying to get the Amulet1 (Async/unclocked ARM from Manchester, back in the day) working as a test project. This, of course, requires Muller C-gate stuff. I'm having a bit of trouble getting it all to work out.

Have you seen any obvious techniques/methods for unclocked circuits that I am probably looking right past?

bra-ket• 11 years ago

it's used by Rex: http://www.theplatform.net/2015/07/22/supercomputer-chip-sta...

trsohmers11• 11 years ago

Hey, CEO of REX here... would be happy to answer questions.

P.S. We're hiring Chisel developers! If you don't know chisel, but want to learn and have RTL experience, we'd love to have you learn on the job! Check out our website: http://rexcomputing.com

Skooma2• 11 years ago

What differentiates your company's Neo Chip vs Adapteva's Epiphany co-processor?

stephenmm5• 11 years ago

Chisel is potentially a revolution in hardware design and I am following it intently but I have not heard of anyone creating an actual chip from a standard fab as of yet. I am trying to make an argument for trying this at my work but I think until we get some more feedback from people in industry it may be too risky of an endeavour. It would be great if you would be willing to share your experiences or know of some papers that would help me build an argument for trying it out.

stephenmm5• 11 years ago

So is the idea that the compiler would try and optimize it so that both code and data would be kept local in the scratchpad memory and if there was a scratchpad "miss" the cores would DMA the needed memory locations from DRAM to the scratchpad?

szabba• 11 years ago

I'm a layman, but the information on your website reminds be both of what GreenArrays are doing and of the 80's INMOS transputers. People might want to know how those compare with what you're working on.

Skooma2• 11 years ago

In my opinion, Chisel feels like "lets write Verilog with Scala syntax." I personally see MyHDL as a better approach as you can leverage existing libraries for generating code (i.e. use scipy to generate the coefficients for your FIR filter). One plus is Chisel generates C++ code for testing your design which is a huge speed increase versus simulating Verilog.

trsohmers11• 11 years ago

The biggest problem with MyHDL in my opinion (As someone using Chisel to make a commercial processor) is its (non existent) "real" simulation capabilities. If something is not cycle accurate (the way that Chisel's C++ simulator is), you can not really be positive of anything...and you don't want to get to physical design and find out you can't meet timing.

gluggymug15• 11 years ago

You saying MyHDL is not cycle accurate? Could you give a citation for that?

cfelton4• 11 years ago

This is ridiculous, you can create cycle accurate (and bit accurate) descriptions in MyHDL. Anyone can verify this themselves by creating an RTL description in MyHDL, convert it to Verilog, and perform a Cosimulation. One can even Cosimulation with the back-annotated layout netlist and verify - yes cycle accurate.

cfelton4• 11 years ago

Here is some information on the speed of MyHDL, http://www.myhdl.org/documentation/performance.html.

Converting to yet another format can be a pain and potentially dangerous, if you are creating a commercial ASIC you need to guarantee each of these formats/representations are equivalent, if there is a discrepancy between the generated C++ and generated Verilog for implementation - oh boy.

jandecaluwe3• 11 years ago

Stop the misrepresentation and do your homework first please. MyHDL is as cycle accurate as Verilog & VHDL. It's based on the same event-driven paradigm - the paradigm that real industrial designers have been using to design real products for two decades. And you do not need conversion to Verilog/VHDL to achieve this - the core of MyHDL is a simulator.

The real difference is that in event-driven languages, clock events are explicit, instead of implicit like in Chisel and the whole array of dead HDLs that preceded it. So if history is any guide, Chisel is dead upon arrival.

nickpsecurity9• 11 years ago

Chisel is a nice toolkit that proved itself in the Rocket processor. One of the more unusual uses of it was Chisel-Q for quantum computing:

http://www.cs.berkeley.edu/~kubitron/papers/qarc/pdf/Chisel-...

Chisel is pretty well-known in academic, hardware community. So, here's a few that you might have not heard of.

Caisson - language-based security meets HDL http://www.cs.ucsb.edu/~chong/papers/109-Caisson-pldi.pdf

SHard - a scheme to hardware compiler http://scheme2006.cs.uchicago.edu/05-saint-mleux.pdf

Cx-Lang - A statically-typed, c-like, HLL for hardware http://cx-lang.org/

Note: I'd love for some people familiar with ASIC or FPGA design to check out Cx-Lang to see if it's good for beginners getting results on FPGA's. The I.P. they sell is so cheap that it's either (a) crap or (b) the result of a productive, synthesis tool (Cx). Just like to know if it's a decent HLS tool compared to FPGA or EDA company offerings. Additional advantage that it's open so it can be reviewed for subversion if one is willing to invest the effort.

gluggymug15• 11 years ago

Just took at look at the cx-lang website. I think it may be too weird for a beginner looking for results. I've been in ASIC & FPGA engineering for 15+ years. The design flow I think they use is more like writing a program that gets translated into hardware. Very different from the regular methodology. Sounds great but there's a big leap between that and getting your FPGA working. For a beginner, it's too much to take on.

I think maybe Chisel and those others would be easier.

nickpsecurity9• 11 years ago

Yeah, I was actually hoping it was a high-level synthesis tool. I appreciate your review on the ease-of-use aspect.

Chisel: Constructing Hardware in a Scala Embedded Language

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