A Brainfuck CPU in FPGA

http://gergo.erdi.hu/blog/2013-01-19-a_brainfuck_cpu_in_fpga/

by gebe • 14 years ago

61 16 14 years ago

gergo.erdi.hu

kimmel• 14 years ago

Every time someone implements something new in Brainfuck it makes me smile.

Where is your god now, high level language snobs? ;)

dons2• 14 years ago

Where? ... Specifying yr cpus, of course...

https://github.com/gergoerdi/brainfuck-cpu-fpga/blob/master/...

iwwr• 14 years ago

[-]>[-]< >+++++++++[<+++++++++>-]<++++++. >++++[<++++>-]<--. >++++++++[<-------->-]<-----. >+++++++++[<+++++++++>-]<---. >+++[<--->-]<. . -. >++++++++[<-------->-]<----. >+++++++++[<+++++++++>-]<+++. >++[<-->-]<-. >+++++++++[<--------->-]<++. >++++++++[<++++++++>-]<+++++++. >+++[<+++>-]<-. >+++++++++[<--------->-]<++. >++++++++[<++++++++>-]<++++. +. . >+++[<+++>-]<++. >+++[<--->-]<--. >++++[<++++>-]<---. >+++++++++[<--------->-]<.

sp332• 14 years ago

Decoder: http://www.iwriteiam.nl/Ha_bf_online.html

StavrosK• 14 years ago

Isn't Brainfuck, pretty directly, a Turing machine? It just has the added complexity of incrementing/decrementing states rather than setting them outright.

jlouis• 14 years ago

It is very close to being a TM, but there are differences, because of the way you describe the DFA in Brainfuck in contrast to a TM.

Also, TMs are not entirely formal in the sense that there exists multiple TMs which all are equivalent - but there is no correct implementation. So when people say TM, or even BrainFuck, then it is not entirely clear what machine they mean.

kryptiskt• 14 years ago

I always liked that Brainfuck was nasty and impractical because it was very simple, and not because it was obtuse like many other esoteric languages.

lawn• 14 years ago

Interesting!

I had a run in with FPGA's in school in a course where we were tasked with building "a digital device". Initially we planned to make a CPU which ran brainfuck, but in the end we made one which ran Redcode and fulfilled the corewars 88 standard [1].

I'm by no means a hardware fantast, but it was still extremely fun to build. We made a microprogrammed processor with accompanied assembler. An exercise I recommend to everyone.

[1] http://stuff.mit.edu/afs/sipb/project/corewars/koth/doc/ICWS...

46Bit• 14 years ago

Definitely agree about building a CPU. I keep meaning to get my hands on a hobbyist FPGA. I used them a little last year before I dropped Uni, and really want to get back to it.

For now I'm satisfying myself with plans for a diode-matrix-microprogrammed CPU :-)

jacquesm• 14 years ago

Digilent has some pretty neat stuff, it beats the crap out of doing your microcode with 1n914s.

greyfade• 14 years ago

This is the indirect goal of the Nand2Tetris curriculum: http://www.nand2tetris.org/

s_kanev2• 14 years ago

I'm a bit surprised by the workflow. While I agree that hardware description languages are terrible from a software developer point of view, to me Verilog is typically much more tolerable than VHDL. Also, in the last few years, SystemC has been getting much more popular as the high-level step before Verilog/VHDL.

supahfly_remix2• 14 years ago

I wondered the same thing. From the github link, I don't see the advantage of Lava over Verilog or VHDL, both languages designed for describing hardware. Maybe Haskell provides some compiler guarantees?

dons2• 14 years ago

Generally, people use these high-level HDLs, like Lava or Cryptol, because:

- faster design time, as you write less code to get the same things done

- reusable high level specifications

- access to high level optimizations not easily possible on the VHDL level

- easier to formally verify the high level spec matches implementation

(Aside, I used to work for a company that designed and sold these types of toolchains).

A Brainfuck CPU in FPGA

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