Scrying the AMD GFX1250 LLVM Tea Leaves

https://chipsandcheese.com/p/scrying-the-amd-gfx1250-llvm-tea

by mfiguiere • 4 days ago

66 10 4 days ago

...not just implementing barriers in hardware but also full monitors, allowing the wave to be notified if a specific cache line is evicted from the L2 cache.

What is this feature for? When do you need it?

dragontamer2• 3 days ago

GPUs are absurdly SMT. Like 8 threads or 10 threads (or tracked instruction pointers) per hardware instruction execution unit (for AMD, the Workgroup Processor, WGP)

I have to imagine that some kind of queue or data structure would benefit from this information. Especially with server GPU tasks staying resident inside of a WGP for literally hours at a time.

WithinReason2• 3 days ago

sure, but what kind?

averne_2• 3 days ago

The explanation is missing that the hardware also notifies you of modifications, which makes it useful for implementing cross-cluster synchronization primitives.

Compare to MONITOR/MWAIT on x86: https://www.felixcloutier.com/x86/mwait#mwait-for-address-ra...

majke• 3 days ago

I'm a heavy user of NVIDIA LOP3 instruction (uint32). I wonder when AMD will finally support it well.

Archit3ch• 3 days ago

I'm very interested in your use case.

I looked into bit-slicing techniques, but they increase throughput at the cost of massive latency. This is not acceptable for realtime audio.

15155• 3 days ago

Fusing multiple boolean logic functions into one.

averne_2• 3 days ago

They already do, it's called v_bitop3_b32. Added in CDNA4, present in CDNA5 and will be making its way in RDNA5, if the LLVM code is to be trusted.

https://www.amd.com/content/dam/amd/en/documents/instinct-te...

androiddrew• 3 days ago

Where does someone start on kernel development for an RDNA4? Books, resources, whatever?

8 year developer just getting into to AI side of the house

Scrying the AMD GFX1250 LLVM Tea Leaves

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