Learn Something Old Every Day, Part XVIII: How Does FPU Detection Work?

https://www.os2museum.com/wp/learn-something-old-every-day-part-xviii-how-does-fpu-detection-work/

by kencausey • 4 months ago

67 8 4 months ago

One small nit:

“it cannot have an FPU added (that is not the case with Cyrix 486S…)”

This is mostly true but the 486SX can be paired with a math coprocessor via the 487SX, but the 487SX is actually a full CPU that disables the SX, not a full FPU!

phire3• 4 months ago

The point is still very valid. You can't add a math coprocessor to the 486SX.

The 487SX is nothing more than a polite fiction to allow consumers (and the computer shops selling to them) to continue their existing habits of buying FPU-less systems, (because most people didn't need FPUs) safe in the knowledge they could buy the upgrade if they ever needed it.

It actually cost the motherboard vendors quite a bit more to wire up the second socket, so obviously there was demand for the flexibility.

timw4mail• 4 months ago

Some 486SX boards are even sillier: There's a soldered 486 SX, and a regular 486 socket, so you can add a socketed 486 SX to your board with a 486 SX. Obviously the point is to be able to add a regular 486 CPU, but it's still amusing.

userbinator2• 4 months ago

Speaking of recent x86 processors with an FPU, it's notable that some variants of the https://en.wikipedia.org/wiki/Intel_Quark were basically a 486SX core with some Pentium instructions "backported", and hence lack the FPU.

Of course there's also the https://en.wikipedia.org/wiki/Vortex86#Vortex86SX , an interesting legacy from an era when there was far more competition in x86-compatible CPUs.

Aurornis• 4 months ago

Interesting to look back on an era where companies could create an entire CPU and bring it to market with reasonably competitive performance.

CPUs today are so powerful and complex that it takes highly capitalized companies many years and generations to get something that approaches modern performance expectations. Arguably we’re still waiting for a RISC-V CPU to reach the market that has decent performance.

phire3• 4 months ago

Lakemont doesn't actually share much history with the 486SX.

Hard to tell the exact ancestry of Lakemont. It might be a from-scratch scalar design that just so happened to target the i586 instruction set, but with a 486 style 5-stage scalar pipeline. Or it might be forked and hacked down from something more modern, like Atom.

It's a very configurable core. There are versions with just the FPU and NX bit turned off. MCU variant goes further, turning off segmentation, the BCD/string instructions, xchg and the AF/PF flags.

Intel did a talk on the MCU core at hot chips [1], which gives you a better idea of how they made/configured it (but doesn't give much insight into where the original Lakemont core came from).

But modern hardware design acts kind of like software these days. They write verilog code, they fork designs off, they share code or entire modules between teams. The code is often configurable. And then they throw the code + configuration at automated tooling which spits out reasonably good gate layouts.

[1] https://www.youtube.com/watch?v=LHYBPhKRlVM

userbinator2• 4 months ago

They reused the diagrams (and much of the text) from the 486 era for the Quark documentation, which I think wouldn't happen if they weren't reusing the core design. I remember an early datasheet had "QuarkDX" show up a few times.

Learn Something Old Every Day, Part XVIII: How Does FPU Detection Work?

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