Understanding x86_64 Paging

https://zolutal.github.io/understanding-paging/

by signa11 • 3 years ago

166 23 3 years ago

zolutal.github.io

LAC-Tech• 3 years ago

Very cool. I've actually been trying to learn about this area recently. I know this was aside from the main thrust of the article, but this but made me think:

Page Cache Disabled (PCD) – pages descendant of this PGD entry should not enter the CPU’s cache hierarchy, sometimes also called the ‘Uncacheable’ (UC) bit.

I guess this is some optimisation where it's decided the page isn't worth taking up valuble CPU cache state. And now I'm wondering what this algorithm is that decides it..

mark_undoio• 3 years ago

My guess is that this is useful when interacting with memory-mapped IO devices - individual accesses can have meaning at the device level, so you don't want the caches getting in the way (and e.g. removing / combining accesses or providing stale data).

kimixa2• 3 years ago

Also useful for memory you know you won't be touching multiple times and just thrash the cache.

For example GPU drivers and texture copying - even on integrated GPUs that have cache coherency with the CPU (so don't "need" to manually flush it), there's no point filling the CPU cache with data you're only touching once with effectively a memcpy() on the CPU, you'll just evict more useful data you'll probably need to readback after anyway.

PhilipRoman• 3 years ago

I don't think it's an optimization, for that you would typically use non-temporal instructions which avoid polluting cache with one-off accesses.

ithkuil• 3 years ago

Is this useful for memory mapped IO?

loeg5• 3 years ago

UC is for MMIO.

foobiekr• 3 years ago

It's for mapped I/O primarily.

commandersaki• 3 years ago

This is great. I find the x86_64 paging to be very similar to RISC V which I was exposed to poring through xv6 code.

snvzz• 3 years ago

There's definitely both "established best practices" and many other legacy ways to do things on x86.

RISC-V is quite boring, majorly opting for well-proven approaches. And a lot of its technical value comes from doing just that.

Yet x86-64 and ARM would have a hard time justifying their complexity, when RISC-V achieves the same with simplicity, and matches or beats them on objective metrics[0].

0. https://dl.acm.org/doi/pdf/10.1145/3624062.3624233

phendrenad2• 3 years ago

Easy on paper, hard to get right when trying to do this in C or Rust!

drxzcl• 3 years ago

It diverges more from x86 than I would have expected!

codeflo• 3 years ago

I’m not deeply familiar with either, though I have written a toy x86_64 bootloader once. There are more levels in x86_64 (which makes sense to me that a larger address space would benefit from a sparser encoding). What else is significantly different?

loeg5• 3 years ago

x86 in some modes (PSE but not PAE) has 4MB superpages, whereas in PAE mode or in x86_64 they're 2MB (first level). That's the only one I remember off-hand.

bhakunikaran• 3 years ago

Really enjoyed this deep dive into x86_64 paging.

Understanding x86_64 Paging

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