Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer

https://www.righto.com/2023/08/datapoint-to-8086.html

by matt_d • 3 years ago

135 49 3 years ago

righto.com

kens12• 3 years ago

Author here if you have questions about the Datapoint 2200 :-)

pwg• 3 years ago

Ken, you have this statement in a footnote:

I haven't been able to find any instruction set before the Datapoint 2200 that required memory addresses to be loaded into a register.

For a direction to look, look at the CDC mainframes (the Cybers, the 6600 and 7600 models, and possibly earlier models). A too great many years ago now while in college for my EE degree the college had a pair of CDC's (I think a 6600 and 7600, I only ever had access to the older one for a mandatory "assembly programming" class) and one of the 'quirks' of the CDC CPU design was that the CPU had (if memory serves) eight data registers and eight address registers, and to perform a memory read, one loaded an address into one of the first six address registers, which would cause a memory read from that address, storing the result in the corresponding data register (so A0 caused a read into D0, etc.).

For a memory write, one loaded an address into either A6 or A7, which caused the CPU to perform a memory write using data from the corresponding data register (A7 caused D7 to be written to memory).

The "production dates" for these CDC systems is relatively contemporary (for a reasonable fudge factor around "contemporary") with the Datapoint terminal, so these might be an example of another architecture from a similar time range (or quite possibly before) that loaded an address into a register in order to access memory.

kens12• 3 years ago

Thanks, that's very interesting and I've updated the footnote. I looked at the CDC 6600 manual and it works pretty much like you say. If you change an address register A1-A5, the system automatically reads from memory into the corresponding operand register X1-X5. Similarly, if you change address register A6 or A7, the word in X6 or X7 is stored to memory. It is interesting to look at old systems that do things wildly differently from modern computers.

http://www.bitsavers.org/pdf/cdc/cyber/cyber_70/60045000_660...

Animats3• 3 years ago

The CDC 6600 did that for a completely different reason. It's an early superscalar machine. It overlaps memory operations, and even some compute. This is visible to the programmer. The desired programming style is load, load, load, operate, operate, operate, store, store, store. Then the operations can overlap. There's something called the "scoreboard" to stall the pipeline if there's a conflict, but there's no automatic re-ordering.

The tiny machines at the Datapoint 2200 and 80xx level didn't do anything like that.

At the other extreme, there were low-end machines where the registers really were in main memory. The compute/memory speed ratio has changed over time. Today, arithmetic is much faster than memory, but in the late 1960s/early 1970s, arithmetic was often slower than memory on low-end machines.

adrian_b2• 3 years ago

No questions, just thanks for another interesting article.

What I have found especially interesting is the story about the undocumented instructions of 8085, because I was not aware of them.

Those instructions would have been actually quite useful and if they had been documented they would have made the Intel 8085 significantly more competitive with Zilog Z80, taking into account also the fact that in the early years 8085 usually had a higher clock frequency (3 MHz or 5 MHz for 8085 versus 2.5 MHz or 4 MHz for Z80).

When I was young I have worked to make some improvements in speed to the functions that implemented the floating-point arithmetic operations in the run-time library used by the Microsoft CP/M Fortran compiler, because they were too slow for my needs (obviously after disassembling them, as Microsoft did not document them). On an Intel 8080 CPU, more than 100 FP64 multiply-add operations per second was considered as high speed, while now a CPU that does 100 billion FP64 multiply-add operations per second is considered a very slow CPU (the best desktop CPUs are more than 6 times faster).

I am sure that with the extra 16-bit operations provided by 8085, a decent speed-up of those FP arithmetic functions would have been possible and I would have found that useful at that time, because I was able to use IBM PC clones only some years later.

drallison2• 3 years ago

The undocumented instructions in the 8085 were described in detail in Dr Dobb's Journal shortly after announcement of the 8085 (with no mention of the "new" instructions).

canucker2016• 3 years ago

Was the datapoint 2200 a brand new machine or was it influenced by others esp. wrt. the assembly language instruction set?

Looking up Datapoint on Wikipedia shows a predecessor box, the 3300. But did the new designers of the 2200 totally ignore the 3300 instruction set? The 3300 seems to have used shift-registers as well.

Other data terminals at that time or radio equipment these designers might have used before?

Thx

https://en.m.wikipedia.org/wiki/Datapoint https://en.m.wikipedia.org/wiki/Datapoint_3300

kens12• 3 years ago

The Datapoint 3300 was strictly a terminal. It was not programmable and did not have an instruction set. It basically had counters for the cursor position and put characters into memory at that position, and had a ROM to generate characters. Manual: http://bitsavers.org/pdf/datapoint/3300/70116_3300termMaint_...

I don't think the Datapoint 2200 had any specific influences, at least none that I could find. Keep in mind that at the time, it was fairly common to make a processor out of TTL chips. People would make a custom processor for random things like a CNC controller or a video game. These processors were usually ad hoc, with an instruction set that had the features that were needed. If people were going to copy something, it was often a PDP-8 or 11 or a Data General NOVA.

AlbertCory4• 3 years ago

hi Ken!

I wrote about DataPoint in The Big Bucks. It turns out I knew Gordon Peterson, architect of ARCNet, so he was a very good source for me.

Naturally, there's a book about them. I read these things so you don't have to.

kragen8• 3 years ago

why did they collapse

it seems like it was only two years from being the darling of wall street to bankruptcy

what happened

Hizonner• 3 years ago

Lessons learned:

1. Incremental, backward compatible progress wins in the market.

2. Incremental, backward compatible progress leads to nasty, ugly, hard to use hacks that create waste, inefficiency, and user pain.

Explains a lot, really.

kens12• 3 years ago

As Intel engineer Tom Forsyth said, "The REAL cost of x86 legacy is not gates, it’s lots and lots of meetings."

nine_k• 3 years ago

Welcome to biological evolution, by the way.

modeless• 3 years ago

You have to measure "waste, inefficiency, and user pain" not in a vacuum but by comparison to the alternative. Breaking backwards compatibility also causes waste, inefficiency, and user pain.

rob74• 3 years ago

Remarkably, Intel has managed to move from 8-bit computers to 16, 32, and 64 bits, while keeping systems mostly compatible.

Well, the move to 64 bit didn't quite turn out as Intel wanted it, and they had to copy AMD's version of it. This is acknowledged in footnote 20, but the article itself sounds like Intel was infallible and never mentions AMD at all...

userbinator3• 3 years ago

I remember reading somewhere that Intel also had a backward-compatible 64-bit extension in development, but was beaten by AMD to it when the Itanic turned out to be a flop.

rep_lodsb2• 3 years ago

Great article, especially the opcode charts! Almost all you find online are unfortunately in hex, which obscures the encoding.

The strangest feature inherited from the 8008 is probably the parity flag. There are some uses other than 7-bit ASCII comms for it, but this kind of code is probably heavily 'pessimized' on modern CPUs:

    TEST AL,0xc0
    JZ   quadrant0    ;both bits clear
    JPE  quadrant3    ;both bits set
    JS   quadrant2    ;only bit 7 set
    JMP  quadrant1    ;only bit 6 set

And to this day, even the reserved lower flag bits have the same values as they did on the 8080 ('S Z 0 A 0 P 1 C'). I wonder if there is actually code out there that depends on bit 1 being set.

One nitpick:

The ModR/M byte has been changed in 64-bit mode so the BX (originally HL) register is no longer special when accessing memory

It was 32-bit mode that made EAX, ECX and EDX usable for addressing, though not the 16-bit lower half registers. And nothing with that changed in the transition to 64 bits.

kens12• 3 years ago

Thanks, I've fixed that.

kragen8• 3 years ago

you might be interested in my opcode map for the 8080 in Dercuano (temporary online copy at https://dercuano.github.io/notes/8080-opcode-map.html ); it not only uses octal but also uses the digit order 0, 2, 4, 6, 1, 3, 5, 7 to bring out the structure of the instruction set better

datapoint's manuals for the 2200 instruction set use octal, but intel's 8008 manual uses hex, maybe due to some kind of misguided admiration for ibm

kens12• 3 years ago

That digit order is an interesting choice to bring out more structure. The downside is the registers and RST instructions get weirdly permuted. (By the way, your link is broken because the closing parenthesis gets appended; I recommend a space before it.)

My suspicion is that Intel's manuals used hex because octal was kind of obsolete by that point.

userbinator3• 3 years ago

I wonder if there is actually code out there that depends on bit 1 being set.

Almost certain there is. Demoscene and emulator detection code come to mind.

watersb• 3 years ago

In 64-bit mode, the 8086's general-purpose registers are extended to sixteen 64-bit registers (and [soon](https://www.intel.com/content/www/us/en/developer/articles/t...) to be 32 registers).

Wait, what?

I thought that Intel AVX10 was limited to vector instructions, but they are re-arranging the instruction set and doubling general-purpose CPU registers.

And adding lots of conditional instructions, so that common loop patterns can be mapped onto a conditional instruction, rather than written out as a branch to another code path.

This architecture extension is called Intel APX, referenced by the AVX10 extension, but I don't recall hearing about it before.

APX will not need any additional hardware space, as they are carving these 64-but registers out of the deprecated MPX registers.

Memory Protection Extension https://en.m.wikipedia.org/wiki/Intel_MPX

kens12• 3 years ago

There was some discussion of APX on HN a couple of weeks ago: https://news.ycombinator.com/item?id=36853166#

userbinator3• 3 years ago

I wouldn't consider little-endian "quirky" --- it's the most logical way to do it, since the significance increases with increasing address. AFAIK all arbitrary-precision arithmetic routines use little-endian ordering even on big-endian machines for this reason, as big-endian requires lots of length-dependent terms in calculation.

When the 8086 was released, these registers were renamed to AX, CX, DX, and BX respectively.

It's worth noting that NEC produced the V25/V35, which were basically binary compatible (with some extensions) to the 8086, and presumably to avoid legal issues (which happened anyway), they renamed the instructions and registers; instead of AX CX DX BX SP BP SI DI, they used AW CW DW BW SP BP IX IY --- the latter two reminiscent of the Z80.

kens12• 3 years ago

You're not going to lure me into a big-endian vs little-endian argument :-)

Aloha• 3 years ago

Without starting the argument, I'd like to know your thoughts - for me as someone who operates several layers of abstraction away from the hardware, the choice seems mostly arbitrary (like Fahrenheit vs Celsius) with each option having both benefits and drawbacks.

tempodox• 3 years ago

The "stopgap" 8086 processor, however, started the x86 architecture that changed the history of Intel.

Nothing lasts longer than a temporary fix.

Tracing the roots of the 8086 instruction set to the Datapoint 2200 minicomputer

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