MDL: A Micro-Architecture Description Language for LLVM

https://discourse.llvm.org/t/rfc-mdl-a-micro-architecture-description-language-for-llvm/66409

by ingve • 4 years ago

157 13 4 years ago

discourse.llvm.org

xiphias2• 4 years ago

The documentation referenced from the mail is here:

https://github.com/MPACT-ORG/llvm-project/blob/work/llvm/doc...

snvzz2• 4 years ago

LoCs of aarch64 vs risc-v is comical.

I wonder what's going on there.

ghotli• 4 years ago

I'm no expert (but I do work with this stuff regularly) and I realize this is gcc documentation vs llvm docs. Regardless, arm32/64 has a lot of optional instruction sets that may or may not be supported on a given processor as improvements have been made over time.

For example, check out the feature modifiers at the bottom of the page here for aarch64: https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/AArch64-Option...

Versus RISC-V: https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/RISC-V-Options...

Arm32 is even more complex: https://gcc.gnu.org/onlinedocs/gcc-12.2.0/gcc/ARM-Options.ht...

drew-y• 4 years ago

Where are you making this comparison from?

Edit. Never mind. Found it. https://github.com/MPACT-ORG/llvm-project/blob/work/llvm/doc...

RISC-V: 104 LoC, AArch64: 3483. That's wild.

tmd83• 4 years ago

Then there's x86: 7406 LoC

KZerda• 4 years ago

Number of variants to a large extent. Risc-V has a relatively few number of implementations that are about the same in terms of how they implement things. Aarch64 has a comparably huge number of implementations that have different pipeline descriptions, different extension APIs supported, etc. Aarch64 includes descriptors for everything from a low-end Cortex A53 designed back in 2012 to a a high-end Apple M2 that was released this year.

Ericson23142• 4 years ago

Born RISC, Died CISC

Will happen to RISC-V too, dontcha worry ;)

snvzz2• 4 years ago

Nah.

RISC-V is already caught up with the important features x86 and ARM have, and still hasn't been corrupted.

It'll endure.

sixstringtheory2• 4 years ago

What kinds of optimizations could be available to a system that can integrate a semantic and systematic understanding of a chip, microarchitecture and high-level compiled languages on top of that?

I know we have e.g. VHDL but to marry that to a high level language compiler seems like it would open some new doors (maybe this has already been done and I’m just not aware).

throwawaylinux• 4 years ago

Compilers have had detailed pipeline and memory hierarchy models available for decades. This is not a new thing in LLVM, the new thing is a language for describing a pipeline (which replaces an older description language).

Instruction generation and scheduling optimizations primarily.

I don't know if much higher level optimization is done, possibly some cache blocking? I don't think the limitation is the hardware description available so much as actually using that to make worthwhile optimizations.

brookst• 4 years ago

Going the other direction, it might allow better optimizations of microarchitectures for known workloads by allowing description and simulation of alternative designs at a high level of abstraction.

sixstringtheory2• 4 years ago

Yes absolutely. Perhaps it could be used to design ISAs or even ASICs from a written program?

MDL: A Micro-Architecture Description Language for LLVM

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