A Hardware Accelerator for Tracing Garbage Collection

https://ieeexplore.ieee.org/document/8416824

by davikrr • 5 years ago

3 2 5 years ago

ieeexplore.ieee.org

jasone2• 5 years ago

Paper URL: https://people.eecs.berkeley.edu/~krste/papers/maas-isca18-h...

jasone2• 5 years ago

This is a cool paper, though it doesn't solve the problem that a general purpose tracing accelerator would have to. In order to handle diverse object/value layouts there needs to be some way of determining from the run-time type which words are references. The type information block (TIB) is a flexible, common solution, yet this paper changes the run-time memory layout to do away with TIBs entirely and instead segregate reference/non-reference words using a bidirectional layout (non-references precede the header, references follow the header). The bidirectional layout is a reasonable approach in many cases, but it is not universally applicable. Therefore I see the accelerator as described to be merely an example of co-designed acceleration. And therein lies the rub with GC acceleration -- there are so many approaches to memory layout that it's difficult to come up with a clean abstraction that can be meaningfully accelerated via special-purpose hardware.

A Hardware Accelerator for Tracing Garbage Collection

Related Stories