MyHDL: Using Python as a hardware description and verification language

https://github.com/myhdl/myhdl

by ofou • 5 years ago

20 15 5 years ago

github.com

shash2• 5 years ago

Previously: https://news.ycombinator.com/item?id=20931307 https://news.ycombinator.com/item?id=8836324

Interesting that it hasn't been commented upon much, and the project seems to not have had any updates since 2018...

ofou• 5 years ago

I agree!

Just the fact that it's capable of translating to VHDL or Verilog makes it very useful. I'm surprised the industry doesn't care too much still.

Rinced• 5 years ago

I can tell you, as someone that had some experience in the industry with this, that the two problems are : - Teach people new paradigms - unfortunately, not all FPGA/Asic devs are fond of OOP nor have python on their abilities - Get further down the rabbit hole of framework debugging. To add a new layer on top of the horrible beasts that Xilinx Vivado/ISE or Intel Quartus are, one must ensure that the work is really going to be faster and more reliable.

In the end, on the most constrained workflows, one would have to verify first the python/HDL code using MyHDL, then verify the generated VHDL using the industry tools, then go through the synthesis and place and route processes, add some verification layers there then test the result.

Convincing a team to accept such a framework takes time and organization.

IshKebab4• 5 years ago

The industry still heavily uses TCL. TCL!

tails4e• 5 years ago

I use systemverilog daily, and it's very powerful. What does myhdl bring that's a game changer or even significant advantage in practice? SV has quite powerful synatx, especially for verification, and it seems this replicates the basics of that but had to force it into an imperative box by using yield, etc to achieve concurrence, while SV has it by default - so SV is less complex in thst regard. Its an impressive achievement nonetheless, but I'm looking for a reason to switch.

FPGAhacker• 5 years ago

For rtl there doesn’t seem to be much reason to use things like hardcaml and chisel.

Testing is usually where the claimed advantage is. That and being open source.

But as you say, SV is all about testing and verification. But the tools are closed source and expensive.

I think the big win is the open source tooling that comes along with these efforts.

IshKebab4• 5 years ago

SV has some quite crazy features and is absolutely massive. But I agree I think Python is a terrible replacement. By moving away from SV you lose a lot of tool support which is extremely important (can you do FPV in Python?) and Python is a pretty bad language anyway compared to its peers (Typescript, Kotlin, Rust, etc.)

itsrainingagain3• 5 years ago

I use VHDL, not used Python. My understanding is that Python will be many times slower than VHDL, so verification tests that take the best part of a week would then take several weeks with Python. And being dynamically typed is fine if you are running a script that returns quickly, but what about it borking even hours into a simulation, when you can catch most dynamic type errors with stronger typed languages at compile time. Python doesn't look like a compelling replacement for VHDL, unless my understanding is off.

mst_moonshine• 5 years ago

Using modern languages for hardware design seems to be a tendency today. I wonder how does MyHDL compare to Chisel? Chisel is another hardware description language based on Scala, which has already been wildly used in the RISC-V community. Check it out here: https://www.chisel-lang.org

shash2• 5 years ago

And I've been involved in a project that's making heavy use of Bluespec: https://github.com/B-Lang-org/bsc/

Same problem though - you have to transpile it down to Verilog to use it in anything beyond a simulation.

therealchiggs• 5 years ago

Writing verification in Python is a powerful productivity enhancement. I’m less convinced about the benefits of coding RTL in Python. As others have alluded to, there are strong downsides to adding another layer of tooling into an already fragile tool stack. At some point you’re going to hit proprietary tools that take [System]Verilog or VHDL so a traditional HDL inevitably becomes your base language for synthesis, linting, reference point for constraints etc. My preferred flow is SV for design and C++ (via Verilator) and/or Python (via Cocotb) for verification.

What I find surprising is how the industry seems to have dropped the ball in terms of languages. The biggest innovation in the last 20 years was SystemVerilog, but that combined relatively powerful verification advances with half-hearted improvements to the synthesizable subset of the language. All hardware designers really need is an improved way to abstract design composition - let me pass types, modules and instances around so that I can write composable designs. Instead we got multiple features with narrow special case definitions in the form of interfaces, packages and classes with the result that it’s still very hard to write a function that can be parameterized on type or width and will synthesise?!

The lack of clarity about what is synthesizable means different tools have different levels of language support. Any reasonably complex project will utilise multiple tools so you have to code to the lowest common denominator (after working out by some painful process which language features work reliably in each tool). The combined tax on the tool vendors (most of whom took the best part of a decade to get SystemVerilog support) and designers must total hundreds of thousands of developer hours in wasted productivity. I wish we had separated out verification from HDL a long time ago. Verification is essentially just software, why should it share the same language as the hardware design?

MyHDL: Using Python as a hardware description and verification language

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