Getting 4 bytes or a full cache line: same speed or not?

https://lemire.me/blog/2018/07/31/getting-4-bytes-or-a-full-cache-line-same-speed-or-not/

by ingve • 8 years ago

39 18 8 years ago

Const-me7• 8 years ago

I don’t like the article.

The code is not portable to other compilers/OSes so I can’t even run it here on Windows. The code uses inline assembly a lot, i.e. optimizer likely failed to achieve much, and for code like this optimizations are very important.

The reason for inline assembly is also worse mentioning, it’s for rdtsc instruction. Mainstream CPUs have dynamic frequency for the last decade. Recent CPUs return rdtsc values unrelated to the count of instruction it executed, it’s a counter running at some constant frequency. The code uses AVX, the CPU is therefore at least sandy bridge or AMD equivalent. Now in 2018, __asm rdtsc is no longer a good method for performance measures.

londons_explore• 8 years ago

You don't need to use rtdsc for this... You can use any library/os specific timing functions. Timing accuracy doesn't even really matter because you can just do more iterations.

Since it's outside the main loop, it shouldn't affect compiler optimizations.

justrobert2• 8 years ago

I'd say if you're interested in performance to this level, it is useful to know both at&t inline asm syntax on top of the simpler microsoft inline asm syntax.

ordu4• 8 years ago

The code uses inline assembly a lot, i.e. optimizer likely failed to achieve much, and for code like this optimizations are very important.

Yes, optimizations are important, but not for the question the autor tries to ask. To answer his question he need to control optimizations, to have vectorized code and not vectorized one. The simpliest way to control optimizations is to turn them off and to do them by hand.

Recent CPUs return rdtsc values unrelated to the count of instruction it executed, it’s a counter running at some constant frequency.

So this counter is the best fit to measure speed of code. What the point to count number of instructions executed when different instructions take different time to execute? But if rdtsc counts clock ticks, than it fits best. It is OS independant way to measure time. It is compiler dependant way, but it works with gcc and clang, the compilers you can get for free. Alternatively it is not so hard to rewrite two non-empty __asm statements into any asm syntax your compiler understands. There are total of 6 instructions.

justrobert2• 8 years ago

Often you can turn off frequency scaling so you can have rdtsc still be useful.

Const-me7• 8 years ago

it works with gcc and clang, the compilers you can get for free

When I’m building for Windows, I usually use Visual C++ 2017 community edition, the compiler I got for free.

into any asm syntax your compiler understands

When building 64 bit binaries, my compiler doesn’t understand any syntax. The portable way to produce that instruction is __rdtsc() intrinsic, it’s supported in all major compilers just in different headers, x86intrin.h for gcc/clang, intrin.h for msvc.

There are total of 6 instructions.

Right, but I’m not sure assembly, inline or not, has good compatibility with advanced optimization techniques implemented by all modern compilers. It’s just too low level: harder to inline, impossible to move stuff across registers…

lscharen• 8 years ago

To me, the takeaway is that there is a ~10x performance difference between the near-worst case memory access pattern (330 cycles) compared to the best using SIMD (41 cycles).

A potential order of magnitude improvement hiding in the memory access patterns of your code makes this worthwhile information for a lot of devs.

corysama• 8 years ago

Additionally, if you do the wait for a byte, you've done 90% of the wait for 63 adjacent bytes. Software becomes memory bound when it peeks at 4 bytes here, 4 bytes there in zillions of unpredictable cache lines. So, instead of waiting 41 cycles to process 64 bytes, it waits 300 cycles to process 4.

It helps to think of the * and -> operators in C++ as "int cache64BytesAndLoad4FromCache(int *p);" That's when you start to really feel "int x = a->b->c->d; a = a->next;" deep in your gut.

mjw10072• 8 years ago

When 'percache' is higher, there will be more instructions executed between calls to pick_address_of_random_cache_line().

That means as the out-of-order processor "runs ahead" while waiting for the first main-memory request, it will make fewer requests to main memory before it runs out of space in its reorder buffers, and so it won't be able to overlap so many main-memory requests.

I think this is the main effect they're seeing. It would fit in with SIMD code giving better results, and it explains why the effect mostly goes away when they make each load depend on the previous calculation.

Const-me7• 8 years ago

No it’s not that. The CPU runs fine, the OP was screwed up by GCC optimizer. With MSVC, there’s very small difference when testing with 8GB vectors, only 8% between 1 and 16.

Here’s my portable version, scalar-only, C++, and slightly more optimized: https://github.com/Const-me/MemoryAccessCosts

The results are in result-gcc.txt and result-msvc.txt in that repo. They’re from the same PC, I’m using gcc 5.4.0 running in WSL.

mjw10072• 8 years ago

I think those results just show that if you persuade the autovectoriser to work you'll get the same result as for manual SIMD code, as you'd expect.

Getting 4 bytes or a full cache line: same speed or not?

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